language: VHDL
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Language:
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VHDL
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Package:
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ALLIANCE
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Version:
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1.1
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Parts:
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compiler, simulator, tools and environment, documentation
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Author:
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?
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Location:
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ftp://ftp.ibp.fr/ibp/softs/masi/alliance/
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Description:
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ALLIANCE 1.1 is a complete set of CAD tools for teaching
Digital CMOS VLSI Design in Universities. It includes VHDL
compiler and simulator, logic synthesis tools, automatic place
and route, etc... ALLIANCE is the result of a ten years effort
at University Pierre et Marie Curie (PARIS VI, France).
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Ports:
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Sun4, also not well supported: Mips/Ultrix, 386/SystemV
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Discussion:
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alliance-request@masi.ibp.fr
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Contact:
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cao-vlsi@masi.ibp.fr
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Updated:
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Febuary 16th, 1993
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Language:
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VHDL
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Package:
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VHDL Object Model (VOM)
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Version:
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1.0
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Parts:
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parser
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Author:
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David Benz <dbenz@thor.ece.uc.edu> and
Phillip Baraona <pbaraona@thor.ece.uc.edu>
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Location:
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ftp://thor.ece.uc.edu/pub/vhdl/tools/vhdl-object-model.tar.gz
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Description:
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VOM 1.0 is an object-oriented syntactic specification for VHDL
written using the REFINE software design and synthesis
environment. In simpler terms, it is a VHDL parser which builds
an object tree from VHDL source code.
If you are interested in transforming VHDL into some other form
(source code, whatever) you might be interested in this. The
parse tree (in the form of an object tree) is provided, you would
just need to add your own transformations.
VOM isn't complete. The semantic information is not included
(type checking, certain syntactic-rules, etc.). VOM 1.0 should
parse most VHDL programs. However, it will not detect errors
such as a wait statement in a process statement with an
explicit sensitivity list.
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Updated:
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November 1st, 1994
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