category: electrical engineering languages

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Description:	These are languages used for simulating, designing, and specifying circuits.

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tool: ALLIANCE

tool: Berkeley EDIF200

language/tool: CASE-DSP / Ptolemy

language/tool: SAOL / saolc

language/tool: SASL / Tim Budd's C++ implementation of Kamin's interpreters

tool: SPAM

language/tool: VHDL / VHDL Object Model (VOM)

language/tool: Verilog / XNF to Verilog Translator